When designing an electronic circuit board, consideration for avoiding crosstalk between two or more wires (i.e., wiring) caused by the electromagnetic induction phenomenon is required.
For instance, in an engine electronic control unit (i.e., engine ECU) installed in a vehicle, a mixed arrangement (i.e., layout) of noisy wiring, which may transmit a digital signal, and sensitive wiring, which may transmit a sensor signal (i.e., usually a weak signal), on one wiring board may present a crosstalk-prone condition. The engine ECU already having many components in a small area is further reduced in size to be squeezed into a small space in a vehicle, thereby forcing the wiring board to have a high-density arrangement of electronic components. Further, an increase of a clock frequency of a microcomputer, which is required in pursuit of a higher speed processing in the microcomputer and of sophistication of the engine ECU functions, may increase the change of crosstalk (i.e., make the crosstalk-prone condition worse).
Conventionally, when an electronic circuit board is manufactured, a crosstalk problem in a trial product stage has been resolved in a trial-and-error method. The trial-and-error method designs a new layout of wiring and evaluates the crosstalk of the newly-designed layout of wiring. However, by such repetition of trials and errors, the development period and the number of manufacturing steps are increased for designing and manufacturing the electronic circuit board such as an engine ECU. Therefore, a new wiring design method, which takes into consideration crosstalk prevention in the first stage of laying out the designed electronic circuit on a wiring board, needs to be developed as a design methodology.
In a related field of large-scale integration (LSI) layout design, a crosstalk-considered wiring method is disclosed in Japanese Patent Laid-Open No. 2006-155120 (JP '120).
FIGS. 14A and 14B are illustrations describing the wiring method disclosed in JP '120, which is in regards to a flow of each of the processes performed by a wiring apparatus 130 (FIG. 14A) and two spacing conditions for adjacent wires (FIG. 14B).
The wiring apparatus 130 includes a wiring process unit 136 that performs a wiring process based on a netlist of a semiconductor circuit. The wiring process first considers a first adjacent spacing condition as a minimum adjacent spacing condition (FIG. 14B). Subsequently, a noise analysis unit 140 extracts an error net causing a noise error by analyzing a noise of the wiring generated by the wiring process unit 136. A wiring condition change unit 142 applies to the error net that is extracted a second adjacent spacing condition defining a wider spacing than the first adjacent spacing condition, and applies to the other nets, the first adjacent spacing condition for performing the wiring process again.
The wiring method shown in FIGS. 14A and 14B first considers the first adjacent spacing condition as a minimum adjacent spacing condition for all of the nets for performing the wiring process, and then extracts an error net that causes a noise error, such as a crosstalk, by performing a noise analysis. The wiring process is then performed again only for the error nets by applying a new adjacent spacing condition that increases the spacing between wires and for the resolution of the noise error.
The wiring method of JP '120 assumes, as a prerequisite, an after-wiring noise analysis. Further, the wiring method is simply replacing the conventional trial-and-error type noise error countermeasure for the trial products with the repetitious trials and errors of wiring layout design and noise analysis on a simulation basis. Therefore, once the error net is extracted in the noise analysis after the wiring based on the first adjacent spacing condition, the re-wiring is required.
In addition, a large number of wire pairs need to be considered for designing the wiring board of the engine ECU. As a result, if the wiring method of JP ' 120 is used for designing the engine ECU, a correction of one error net of the extracted wire pair may cause a change at other portions, and may create a new noise problem for the other wire pair, thereby possibly leading to a “whack-a-mole” kind of analysis and re-wiring cycles leading to an increase of man-hours of the design process.
Further, the wiring method of JP '120 performs the wiring process uniformly to all nets (e.g., regardless of the noisiness or sensitivity of the wire), such as applying the first adjacent spacing condition to all wires, performing a noise analysis, and changing the adjacent spacing condition specifically for a portion having a crosstalk problem. Therefore, regardless of the noisiness or sensitiveness of digital signal transmission wiring and sensor signal transmission wiring, the wiring method of JP '120 does not put not-so-noisy wires or not-so-sensitive wires closer than the first adjacent spacing condition, which should otherwise be more closely arranged. As a result, the size of the wiring board and/or the number of wiring layers are increased.